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High-level modeling using extended timing diagrams - A formalism for the behavioral specification of digital hardware
Auteur(s)
Moeschler, Philippe
Amann, Hans-Peter
Pellandini, Fausto
Date de parution
1993-09-20
In
IEEE Proceedings of the European Design Automation Conference (EURO-DAC), with EURO-VHDL '93, Institute of Electrical and Electronics Engineers (IEEE), 1993///494-499
Résumé
The principles of high level modeling of digital hardware circuits using the extended timing diagrams (ETD) formalism, which adds conditions, events, action expressions, and particular constraints to traditional timing diagrams, are described. Hierarchy and concurrency are also integrated so that a full top-down design becomes possible, enhancing at the same time the readability. While, for simulation purposes, the implementation of the formalism generates behavioral VHDL (VHSIC Hardware Description Language) models, a dedicated high-level translator generates VHDL code for synthesis. Both the ETD formalism and its implementation are part of MODES, a more complex modeling expert system including complementary editors.
Identifiants
Type de publication
journal article
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