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A Low-Jitter and Low-Power CMOS PLL for Clock Multiplication
Auteur(s)
Shi, Xintian
Imfeld, Kilian
Tanner, Steve
Ansorge, Michael
Farine, Pierre-André
Date de parution
2006
In
IEEE Esscirc - Mixed Signal, High Voltage & High Power Circuits, Institute of Electrical and Electronics Engineers (IEEE), 2006/7//174-177
Résumé
This paper describes a phase-locked loop (PLL) designed for clock multiplication in a LVDS transmitter. The PLL consists of a novel low-jitter charge-pump, a fully differential ring-oscillator based VCO, a dynamic-logic PFD, a 2nd order passive loop filter and a digital frequency divider. The PLL exhibits simultaneously low jitter and low power consumption. It has been integrated into a 0.35 µm CMOS process, occupying 0.09 mm2 of silicon area. For a 350 MHz output frequency, the circuit features a cycle-to-cycle jitter of 7.1 ps rms and 65 ps peak-to-peak. At that frequency, the PLL consumes 12 mW from a supply voltage of 3.3 V.
Identifiants
Type de publication
journal article
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