An Automated Design Methodology for the Mapping of DSP Algorithms into Low Power VLSI Architectures
Date de parution
7th International Symposium on IC Technology, Systems & Applications (ISIC-97), Nanyang Technological University, School of Electrical and Electronic Engineering, supported by Institute of Electrical and Electronics Engineers (IEEE), 1997/7/C6/649-652
A design methodology suitable for an effective low power VLSI implementation of a large class of digital signal processing algorithms is presented, which shows to be particularly well-adapted to fulfil the requirements of portable and autonomous microsystems. Starting with the precise specifications of the application algorithms, an appropriate scheduling method is first applied to optimize the dataflow, followed by an assignment method which produces the detailed architecture. The actual VLSI implementation is then performed, resorting to commercial logic synthesis and place&route tools. As an example, the implementation of analgorithm suitable for all-digital hearing aids is discussed. The resulting silicon area is less than 20mm<sup>2</sup> for a 1μm CMOS process, and the measured power consumption at a sampling rate of 16kHz is about 300μW at 1.2V.
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