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An Examination of the Effect of Feature Size Scaling on Effective Power Consumption in Analog to Digital Converters
Auteur(s)
Boyle, Keith
Editeur(s)
Kilambi, Sai Mohan
Dlugosz, Rafal Tomasz
Iniewski, Kris
Gaudet, Vincent
Date de parution
2006-10-03
In
IEEE Workshop on Signal Processing Systems (SIPS), Institute of Electrical and Electronics Engineers (IEEE), 2006/IM4/PT1-2/194-199
Résumé
Wireless Sensor Network (WSN) nodes require components with ultra-low power consumption, as they must operate without an external power supply. One technique for reducing consumption of a system is to scale it to a smaller technology; however, in recent technologies is not clear whether the decrease in dynamic power consumption outweighs the increase in static power consumption (due to leakage currents). Here this is considered by examining the power consumption of three implementations of an analog to digital converter (ADC). One in 350 nm, one in 180 nm, and one in 90 nm, were simulated and compared. The results show that the dynamic power consumption was reduced by a factor of four over the three technologies, but standby power consumption increased by an order of magnitude. The power consumption of the 180 nm implementation was always lower than the 350 nm implementation. However, assuming a WSN application with a duty cycle of 1%, the effective power consumption of the 90 nm ADC was higher than both the 180 nm and the 350 nm implementation. This highlights the dominance of leakage current in determining the effective power consumption in low-throughput nodes.
Autre version
http://www.ieee-sips.org/tp.html
Type de publication
Resource Types::text::journal::journal article
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