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VELOX: An Integrated Approach to Transactional Memory on Multi and Many-core Computers

Titre du projet
VELOX: An Integrated Approach to Transactional Memory on Multi and Many-core Computers
Description
These days everyone wants a “supercomputer” in their pocket. Consumers are demanding more performance and power from smaller and sleeker devices. However, physical size limitations might soon impede the ability of such devices to deliver the expected speed and functionalities. This performance wall represents a serious issue that vendors are addressing through the application of multi-core processors, already in use in some everyday devices such as game consoles or cell phones. However, one key issue has not been addressed yet: writing software for these multi-core platforms (parallel programming) requires specialized skills.

Transactional Memory (TM) is a new programming paradigm that simplifies parallel programming. TM can be implemented in hardware, in software, or as a combination of both. Because transaction block constructs, the cornerstone of TM, are typically provided at the programming-language level, TM support spans across the complete computer stack from applications down to hardware, encompassing language extensions, compilers, libraries, TM runtimes, operating systems and CPUs.

The high-level objective of the EC FP-7 VELOX Project was to deliver the first integrated Transactional Memory (TM) Stack to serve as both proof-of-concept for the TM paradigm and to serve as a platform for future development in the area of Transactional Memory. In addition, the VELOX Project aimed to provide a set of long-term design guidelines for hardware and software systems to improve the efficiency of TM-based applications running on multi-core platforms.
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Statut
Completed
Date de début
1 Janvier 2008
Date de fin
31 Décembre 2010
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Site web du projet
Identifiant interne
27798
identifiant
https://libra.unine.ch/handle/123456789/1653
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Supporting Time-Based QoS Requirements in Software Transactional Memory

2015, Maldonado, Walther, Marlier, Patrick, Felber, Pascal, Lawall, Julia, Muller, Gilles, Rivière, Etienne

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Deadline-aware scheduling for Software Transactional Memory

2011, Maldonado, Walther, Marlier, Patrick, Felber, Pascal, Lawall, Julia, Muller, Gilles, Rivière, Etienne

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FastLane: improving performance of software transactional memory for low thread counts

2013, Wamhoff, Jons-Tobias, Fetzer, Christof, Felber, Pascal, Rivière, Etienne, Muller, Gilles

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Evaluation of AMD's advanced synchronization facility within a complete transactional memory stack

2010, Christie, David, Chung, Jae-Woong, Diestelhorst, Stephan, Hohmuth, Michael, Pohlack, Martin, Fetzer, Christof, Nowack, Martin, Riegel, Torvald, Felber, Pascal, Marlier, Patrick, Rivière, Etienne

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