Generating VHDL-A-like Models Using ABSynth

Moser, Vincent; Nussbaum, Pascal; Amann, Hans-Peter; Astier, Luc; Pellandini, Fausto

doi:10.1109/EURDAC.1995.527454

Generating VHDL-A-like Models Using ABSynth

Author(s)

Moser, Vincent

Nussbaum, Pascal

Amann, Hans-Peter

Astier, Luc

Pellandini, Fausto

Date issued

September 18, 1995

In

IEEE Proceedings of European Design Automation Conference (EURO-DAC) with EURO-VHDL, i, 1995///522-527

Abstract

A method for the graphical specification and the automatic generation of analogue behavioural models is presented. This method has been implemented as a new software tool called ABSynth. The behaviour of the component to model is described as a functional diagram, which is then automatically translated into a VHDL-A-like analogue hardware description language. No syntax knowledge is necessary and the modelling time is reduced.