Analog-Counter-Based Conscience Mechanism in Kohonen’s Neural Network Implemented in CMOS 0.18 μm Technology

In this study, we present a hardware implementation of the conscience mechanism in Kohonen self-organizing maps. The proposed realization of the conscience mechanism is important to the functioning of the neural network as it eliminates so-called dead (inactive) neurons. As a result the network learning, the level quantization error can be reduced. The conscience mechanism and the Winner Take All (WTA) block have been implemented in 0.18 µm CMOS process. The implementation of the conscience mechanism itself occupies 1200 µm2 and its maximum power consumption is 9.5 µW. The WTA block together with the conscience mechanism occupies 0.024 mm2 and dissipates 55 µW.