Study of a VLSI Implementation of a Noise Reduction Algorithm for Digital Hearing Aids

A methodology for meeting the tight constraints in the physical realization of functional blocks for digitalhearing aids was applied to the implementation of a noise reduction system based on lattice structures. This methodologyfully exploits the flexibility of custom VLSI design through a good interrelation among all the steps of the design. Theemphasis was placed in the study of the fixed point quantization effects to find the minimum number of bits and scalingrequired at every point of the algorithm. Based on these results, an estimation of the power consumption and required sil-icon area was done in the case of an implementation using a low power VLSI architecture.