ASIC DSP compiler for optimized synthesis

This paper presents a high level DSP architecture compiler for cycle-constrained filters and datapath applications. The tool offers an easy way to get, from an equation representation of a filter, a synthetisable VHLD description of an application specific DSP architecture. Inputs of the DSP compiler are an equation file to define the filter structure and a resource definition file to specify the available resource units. The equation syntax is very comfortable. Resource mapping, scheduling, binding and furthermore the quantification of each operation is usually performed automatically, but can be controlled by the user. The resultis a very fast filter synthesis time combined with highest flexibility for the users.