Macro-programmable DSP architecture for parallel/pipelined data pathunits, targeted for FFT based algorithms

A macro-programmable DSP architecture is presented, which is very well situated for the implementation of algorithms with regular data flow graphs, like FFTs. A smart grouping of the algorithm together with the macrocode concept reduce drastically the control and address generation overhead of the DSP and shorten the computation time. This is finally manifested in very low-power consumption, small DSP size, high throughput combined with a high flexibility of the DSP architecture.