A Low Power VLSI architecture with an Application to Adaptive Algorithms for Digital Hearing Aids

A new architecture suitable for an effective low power VLSI implementation of a large class of digital signal processing algorithms is presented, which shows to be particularly well-adapted to fulfil the requirements of portable and autonomous microsystems. Starting with the precise specifications of the application algorithms, an appropriate scheduling method is first applied to optimize the data flow. The actual VLSI implementation is then performed, resorting to parameterized cell compilers for the automatic generation of the primary modules. As an example, the implementation of an adaptive spectral sharpening algorithm suitable for future all-digital hearing aids is discussed. The resulting silicon area is approximately 4 mm² for a 1.2 m CMOS process, and the estimated power consumption at a sampling rate of 8 kHz is about 4 mW at 5V (0.65 mW at 2V).