Leakage aware digital design optimization for minimal total power consumption in nanometer CMOS technologies - Schuster, Christian (My University, 2007)
Starting from deep submicron technologies (< 0.13μm), and even stronger in nanometer technologies, static power consumption, due to leaky “off” transistors, is becoming a non-negligible contributor to the total power dissipation. Under this condition, the total power optimization problem changes considerably. The high parallelization approach commonly used today to increase performances, will soon result in power ineffcient designs. Indeed, the static power consumption of the large number of rarely used transistors will highly penalize the total power consumption. The purpose of this thesis is to investigate the inﬂuence of static power on the design methodologies for low power. In particular, the effects of architectural as well as technology modiﬁcations are explored. The use of technology as an optimization parameter has become possible in recent technologies. In fact, they offer different threshold voltages, each one showing a different trade-off between speed and leakage current. In this work, two different frameworks are considered. In the ﬁrst one, both the supply voltage and the transistor threshold voltage are freely tunable parameters. This is the most general case and corresponds to the situation where the designer has the largest freedom. In the latter framework, we assume that the designer cannot change the supply voltage nor the transistor threshold voltage and they are hence considered constants. This case corresponds to the most common one, where the designer has a supply voltage and a technology type (and hence a threshold voltage) ﬁxed by the application and by the devices the circuit has to interface. In both cases, lot of efforts have been put to the development of a handy way to rapidly estimate the total power consumption and consequently easily compare different architectural/technology variants at the early stages of development. Examples, based on multipliers, are used extensively in the whole thesis and, at the end, the presented theory is applied to a real circuit implemented in a 90nm technology by ST Microelectronics. Measurements show a very large variability of the static power over 16 dies manufactured on the same wafer. For instance, the highest static power consumption at nominal condition (Vdd=1V, f=62.5MHz) over the lowest one corresponds to more than a factor of 2.5. Measured data also report multipliers able to work at 210mV for a frequency of 1MHz!
Thèse de doctorat : Université de Neuchâtel, 2007 ; 1927
Keywords: Circuit numérique à faible consommation; puissance statique; courant de fuite; puissance dynamique; tension d’alimentation très basse; multiplicateur; architecture; 90nm; technologie CMOS nanométrique; Low power digital design; static power; leakage current; dynamic power; very low supply voltage; multiplier; architecture; 90nm; CMOS nanometer technology